|
|||||||||||||||||||
 Mixed Signal BIST LogicVision Embedded SerDes Test (EST) EST structurally measures and tests SerDes performance, typically using the standard serial loopback. Unlike conventional specification-based testing, EST performs diagnostic-based tests by analyzing the individual eye parameters that determine signal-eye distortion and the sampling point within the eye. It validates the parameters that a designer considers during a SerDes core design, using circuitry that can achieve unlimited time resolution, at high-speed and low cost. 
LogicVision Embedded PLL Test LogicVision’s PLL BIST provides stand-alone, modular and comprehensive IP for the digital characterization and production test of analog phase locked loops. PLL BIST enables the on-chip testing of critical PLL parameters essential for the success of today’s multi-million gate, timing critical ASICs.
LogicVision 1149.6 Boundary Scan Automatic generation, integration and verification of 1149.6 boundary scan cells. Higher fault coverage and better diagnosis of GHz connections. Quicker, simpler generation of robust circuitry and IC tests.
|
 
Mixed Signal BIST Silicon Debug Yield Enhancement 
Cynthia_Chen@spirox.com.tw Tel. +886-3-5738099 ext. 2029 China Contact:
|
||||||||||||||||||
